Vayavya Labs

DDGen (Device Driver Generator) is Vayavya Labs first generation tool for enhancing the productivity of embedded designers/programmers. As the name suggests the tool aids in generation of device drivers and low level access methods for any device (IC/ASIC/SoC) on any given platform (Operating systems and Processor). The tool (DDGen) automates driver generation by taking in two inputs namely:

 

The device specification and run time specifications are done using formal languages.

 

DDGen helps in reducing the time required for device driver development. The tool articulates the principle of "Spec once and generate many times". The idea is to capture the device (IC/ASIC/SoC) specification once and in the correct format (without the ambiguity as seen in the data sheets, due to the use of an informal language such as English). Every time the device is used in different applications only the specification related to run time environment (software specification) needs to be changed or redefined. This would result in saving substantial amount of time for the design engineers.

Also the IC vendor can reduce his/her support costs (man days/months effort) by recommending their vendors to adopt the tool.

DDGen relies on two inputs namely Device and Programming Sequence (DPS, a formal specification developed by Vayavya Labs which is similar to Verilog or C language) of a device (IC) and "Run Time Software Specification" (RTS, expressed using certain Keywords and constructs). These two inputs are expected to give all the details that a typical driver programmer would need while developing a device driver. Since the inputs are in a formal language a tool can interpret these inputs and then generate a ANSI C compliant driver code.

The heart of the tool is an expert system that acts on two formal input specifications. The different phases of the tool can be described as follows:

 

Yes. We have a version of the tool that supports industry accepted standard IP-XACT (from SPIRIT). Vayavya has developed extensions to current IP-XACT specifications in order to generate device drivers. However, DPS is a proprietary specification developed by Vayavya Labs.

We are now at beta stage where some of the prominent semiconductor vendors are evaluating the tool for deployment in their design flow. Please contact our sales/marketing division (sales@vayavyalabs.com) for more details.

The table below captures some of the features specific to operating system, processor, interface support and the tool release version.

		Release 1.0	Release 2.0
		(Available Now)	Dec 2009
OS	Linux(2.4,2.6.19)	√	√
	DSP-BIOS	√	√
	T-Kernel(iTRON Based)	√	√
	Win CE 6.0	√	√
	VxWorks	√	√
	Symbian	X	√
	Nucleus	X	√
Processors	X86	√	√
	ARM 7	√	√
	ARM 9	√	√
	C5xxx	√	√
	C6xxx	√	√
	MIPS	√	√
Interfaces	I/O Mapped	√	√
	Memory Mapped	√	√
	I2C	√	√
	SPI	√	√
	I2S	√	√
	PCI	√	√
	PCIe	X	√
	USB	√	√
	Ethernet	√	√
	Wireless LAN	X	√

Yes. The Release 1.0 of the tool supports limited types of these drivers. Currently we support only the mass storage, HID class of USB devices. The future versions of tool will support USB host type drivers too.

Yes. We have tested the tool for generating a video driver for custom ASIC targeted for TV applications. An image processing driver is no different from any control driver when looked solely from driver code point of view. One can say that the processing of data (image data) and the way it is sequenced while processing, is what differentiates an image driver from the rest of the drivers. Since DDGen collects the device programming sequence (as part of DPS), and the RTS specification captures the critical parameters of the design, the tool can generate any type of driver.

DDGen does not do anything special for multi-processor architectures as of now. However we do have a command line option that will generate drivers for multiple devices on a single SOC at one go.

Configuration input in RTS can be used to control the generated code to optimize the code for performance or code size. The current version of DDGen has only limited set of configuration options, and optimizations for power are not supported. The next version of DDGen will provide additional options for optimizations.

The optimal use of DDGen is for writing (generating) device drivers for new systems. However customers who would like to port their existing drivers from one OS to another OS can also use DDGen to reduce the engineering effort and costs. The steps followed in such cases are:

• Write the DPS and RTS by looking at the datasheets and design documents
• Use the tool to generate new set of drivers

In the event of non-availability of device data sheet and design documents Vayavya’s application team can help customers to re-construct the DPS and RTS files from the existing driver and firmware source code base

We strive to ensure that the generated code is of high quality. The tool is checked with a representative set of DPS/RTS inputs. The following checks are in place in our regression workflow:

• Turn on all warnings (e.g, -Wall option of gcc) and ensure that the compiler reports zero warnings
• Compare the generated output with a golden reference code, and ensure no differences are present. The golden reference code has been pre-tested on board and is known to work correctly.
• Check for memory leaks in the driver code with Valgrind

Our internal evaluations show that the engineers can pick up this language within 3-4 days after the training by our Field Application Engineers. DPS is more of a specification language than a programming language, and borrows many of its keywords and constructs from the popular hardware descriptor languages and C- Programming language that IC/SW engineers are familiar with. RTS is similar in syntax to a configuration file - it is a simple task to edit/write it with help of the reference manual.

DPS is easy and a formal way to express the device specification. Currently the device (IC) specification is being done by the IC engineers using English as the medium of communication. This, many a times, results in translation errors and misinterpretation by IC users. Formal specification would remove any such ambiguity and also pave way for automation of laborious work flows. Using DPS not only aids device driver generation but in future it will aid verification test vector generation, which is an important design activity for IC design flow. The net result of all this is significant time gains in product roll out.

The current demo version (Release 1.0) does not have GUI support. However Release 2.0 version, scheduled for Dec 2009, will support a GUI, enabling the users to edit contents of DPS and RTS files, without knowing the syntax details.

Tables shown below give details about productivity improvement, code size for the device drivers generated using DDGen. The matrices below are from some of the BETA customer sites.

ACTIVITY / DEVICE	DMA	I2C(Master)	IR	Timer	Video Backend
Manually Written Driver
Total duration (days)	25	15	18	20	35
Lines of Code (including project common code)	2424	2020	1749	1850	7704
Target compiled EXE size	19.9K	29.7K	22.5K	35K	77.3K
Using DDGen
Writing DPS and RTS (days)	8	6	4	4	12
Validating the driver code for functionality(days)	4	2	2	2	3
Integrating with existing driver environment (days)	1	1	1	1	2
Total duration for automated driver generation (days)	13	9	7	7	17
LoC	1796	1112	1161	618	2540
Target compiled EXE size	26.2K	6.7K	11.5K	5.7K	N/A
% Effort and Time savings	48%	40%	61%	65%	51%

Table 1: Customer - 1, SoC for Digital Television

 

 

ACTIVITY / DEVICE	DMA	Intrupt Controller	Event Router	Clock Generation Unit
Manual Writing of device driver
Total effort for writing, testing and validation of driver (days)	25	21	12	73
Lines of Code (without project common code) (days)	1133	318	1010	3930
Driver Generation using DDGen
Writing of DPS and RTS (days)	6	5	4	20
Driver testing and validation (days)	6	4	3	12
Total duration for driver development (days)	12	9	7	32
Number of lines of code	1381	396	6338	4375
% Effort and Time savings	52%	57%	42%	56%

Table 2: Customer - 2, SoC for Mobile Audio platform

 

Most of the generated code is ANSI-C and is not specific to a processor architecture/tool-chain. However, some sections of the code are based on a specified tool-chain. The user can select the processor and tool-chain to be used, by editing the RTS (Run Time software Specification)

The tool generates human readable code. Comments are generated to describe the functionality of the generated code, indentation is maintained, and the function names in the generated code map to the constructs in DPS.

The goal of DDGen is to generate a complete driver, not just a template/skeleton file that the user has to edit later. DPS captures the complete specification as is required for generation of device driver based on a single device. However, in case of aggregate device drivers (drivers that use services from other devices/drivers), editing the generated code will be required.

The functionality of the APIs are implemented in what is called a "feature" in the DPS file. The name of the feature along with the input and output parameters determine the API signature that will be generated.

The information pertaining to the APIs generated by DDGen in terms of parameters passed, return type and the functionality of the API can also be extracted by "doxygen".

Since the final source code can be edited directly, it is possible to change the signature/implementation of the generated function. However, this approach is not recommended - changing the corresponding sections in the DPS file is preferred.

Vayavya labs offers following licensing models.

• DDGen Standard: The tool is comes with a single OS and processor support which can be selected by the customer.
• DDGen Advanced: In this model the customer can select one or more OS, processor support as per their device requirements. There is an add-on cost associated with every additional OS and processor support that is selected by the customer.

Above mentioned licenses are offered in 3 categories:

• Single user license ( node locked to a PC)
• Bundled (3 user) license ( node locked or floating)
• Enterprise (10 user) license (node locked or floating)

Besides these there are custom licensing models to suit specific needs of the customer. For example a customer can select a list of ICs (devices), platforms (processors) and operating system support and then license the tool on per project basis. In such cases the licensing terms and conditions, and pricing will be worked out separately.

The cost of a license depends on the type of license (check above FAQ for details on licensing models). Additionally Vayavya allows for a flexible licensing mechanism wherein a customer can, (at a very high level) define his licensing components (OS support, Processors, interface requirements). The cost for such license will be worked out on individual basis.

Please contact sales@vayavyalabs.com for further details.

A typical license will carry a free technical support (over email/telephone) for a period of 3 months from the date of purchase of the license. In addition to this, there will be an on-site training given by our field application engineering team on usage of the tool, writing the DPS and RTS files. This training will be for 2 days. The product license also carries user manuals example code (DPS and RTS).

In addition to this, customers can opt for a paid support. This involves the following:

• Availability of an on-site application engineer charged by per man hour rate (typically for one month). The travel and lodge costs of the engineer to borne by the customer
• An off site application engineering support where our engineering team will help specific device/software related queries and also debug the generated driver code (if required).
• Annual maintenance contract where Vayavya Labs will support the licenses with software upgrades, bug fixes, and additionally the telephone and email support for the licensed product is extended for one year

We keep adding different OS support into the tool as we make updated release of the tool. Adding a support for any new OS into the tool is matter or 6~8 weeks time line.

However if a customer is interested in licensing the tool for a particular OS development activities can be expedited.

Our aim is to simplify the device driver writing and help embedded firms to save on their investments on driver/firmware development costs and timelines. Vayavya can deploy the tool internally to deliver your firmware/driver requirement. We will pass on the benefits of cost and time to your projects. By this way you save on upfront investments in tool and also benefit from savings on development and quicker delivery.

In order to evaluate DDGen please write to us at sales@vayavyalabs.com

Alternatively you can also request the evaluation copy of DDGen from our web site

http://www.vayavyalabs.com/download.html

You could also get in touch with us on telephone at +91-831-2463525.

Please note that, as part of evaluation our sales team will collect certain information like: the primary focus of your firm, size of embedded systems teams at your organization, number of drivers handled by your teams, processor, device, interconnects used in your organization or by your team.

Once you sign up for DDGen evaluation you will get a dedicated point of contact for support. Alternatively you could always contact us in the following ways:

E-mail: support@vayavyalabs.com      Telephone:+91-831-246 3525      Fax:+91-831-421 2584